в новой реве было много изменений в памяти.
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28 28 // much empty space
29 29
30 30
31 +
31 32 //0x005F6800 SB_C2DSTAT RW ch2-DMA destination address
32 33 u32 SB_C2DSTAT = 0;
33 34 //0x005F6804 SB_C2DLEN RW ch2-DMA length
...
327 328 u32 sb_ReadMem(u32 addr,u32 sz)
328 329 {
329 330 u32 offset = addr-SB_BASE;
331 + register u32 rflags;
332 + RegisterStruct* reg;
330 333 #ifdef TRACE
331 334 if (offset & 3/*(size-1)*/) //4 is min allign size
332 335 {
...
335 338 #endif
336 339
337 340 offset>>=2;
341 + reg = &sb_regs[offset];
342 + rflags = reg->flags;
338 343
339 344 #ifdef TRACE
340 - if (sb_regs[offset].flags & sz)
345 + if (rflags & sz)
341 346 {
342 347 #endif
343 - if (sb_regs[offset].flags & REG_READ_DATA )
344 - {
345 - if (sz==4)
346 - return *sb_regs[offset].data32;
347 - else if (sz==2)
348 - return *sb_regs[offset].data16;
349 - else
350 - return *sb_regs[offset].data8;
348 + #ifdef SB_MAP_UNKNOWN_REGS
349 + if(reg->unk)
350 + log("Read from unk-mapped SB reg : addr=%x\n",addr);
351 + #endif
352 +
353 + if (rflags & REG_READ_DATA )
354 + {
355 + switch(sz)
356 + {
357 + case 2:
358 + return *reg->data16;
359 +
360 + case 4:
361 + return *reg->data32;
362 +
363 + default:
364 + return *reg->data8;
365 + }
351 366 }
352 367 else
353 368 {
354 - if (sb_regs[offset].readFunction)
355 - return sb_regs[offset].readFunction();
369 + if (reg->readFunction)
370 + return reg->readFunction();
356 371 else
357 372 {
358 - if (!(sb_regs[offset].flags& REG_NOT_IMPL))
359 - EMUERROR("ERROR [readed write olny register]");
373 + if (!(rflags& REG_NOT_IMPL))
374 + EMUERROR("ERROR [readed write olny register]\n");
360 375 }
361 376 }
362 377 #ifdef TRACE
363 378 }
364 379 else
365 380 {
366 - if (!(sb_regs[offset].flags& REG_NOT_IMPL))
381 + if (!(rflags& REG_NOT_IMPL))
367 382 EMUERROR("ERROR [wrong size read on register]");
368 383 }
369 384 #endif
370 - if ((sb_regs[offset].flags& REG_NOT_IMPL))
371 - EMUERROR2("Read from System Control Regs , not implemented , addr=%x",addr);
385 + if ((rflags& REG_NOT_IMPL))
386 + EMUERROR2("Read from System Control Regs , not implemented , addr=%x\n",addr);
387 +
372 388 return 0;
373 389 }
374 390
375 391 void sb_WriteMem(u32 addr,u32 data,u32 sz)
376 392 {
377 393 u32 offset = addr-SB_BASE;
394 + register u32 rflags;
395 + RegisterStruct* reg;
378 396 #ifdef TRACE
379 397 if (offset & 3/*(size-1)*/) //4 is min allign size
380 398 {
381 399 EMUERROR("unallinged System bus register write");
382 400 }
383 401 #endif
384 - offset>>=2;
402 +
403 + offset>>=2;
404 + reg = &sb_regs[offset];
405 + rflags = reg->flags;
406 +
385 407 #ifdef TRACE
386 - if (sb_regs[offset].flags & sz)
408 + if (rflags & sz)
387 409 {
388 410 #endif
389 - if (sb_regs[offset].flags & REG_WRITE_DATA)
390 - {
391 - if (sz==4)
392 - *sb_regs[offset].data32=data;
393 - else if (sz==2)
394 - *sb_regs[offset].data16=(u16)data;
395 - else
396 - *sb_regs[offset].data8=(u8)data;
411 + #ifdef SB_MAP_UNKNOWN_REGS
412 + if(reg->unk)
413 + log("Write to unk-mapped SB reg : addr=%x,data=%x\n",addr,data);
414 + #endif
415 +
416 + if (rflags & REG_WRITE_DATA)
417 + {
418 + switch(sz)
419 + {
420 + case 2:
421 + *reg->data16=(u16)data;
422 + return;
423 +
424 + case 4:
425 + *reg->data32=data;
426 + return;
427 +
428 + default:
429 + *reg->data8=(u8)data;
430 + return;
431 + }
432 +
397 433 return;
398 434 }
399 435 else
400 436 {
401 - if (sb_regs[offset].flags & REG_CONST)
402 - EMUERROR("Error [Write to read olny register , const]");
437 + if (rflags & REG_CONST)
438 + EMUERROR("Error [Write to read olny register , const]\n");
403 439 else
404 440 {
405 - if (sb_regs[offset].writeFunction)
406 - {
407 - sb_regs[offset].writeFunction(data);
441 + if (reg->writeFunction)
442 + {
443 + reg->writeFunction(data);
408 444 return;
409 445 }
410 446 else
411 447 {
412 - if (!(sb_regs[offset].flags& REG_NOT_IMPL))
448 + if (!(rflags & REG_NOT_IMPL))
413 449 EMUERROR("ERROR [Write to read olny register]");
414 450 }
415 451 }
...
418 454 }
419 455 else
420 456 {
421 - if (!(sb_regs[offset].flags& REG_NOT_IMPL))
457 + if (!(rflags & REG_NOT_IMPL))
422 458 EMUERROR4("ERROR :wrong size write on register ; offset=%x , data=%x,sz=%d",offset,data,sz);
423 459 }
424 460 #endif
425 - if ((sb_regs[offset].flags& REG_NOT_IMPL))
426 - EMUERROR3("Write to System Control Regs , not implemented , addr=%x,data=%x",addr,data);
461 + if ((rflags & REG_NOT_IMPL))
462 + EMUERROR3("Write to System Control Regs , not implemented , addr=%x,data=%x\n",addr,data);
427 463 }
428 464
429 465 u32 SB_FFST_rc;
...
445 481 log("SOFT RESET REQUEST FAILED\n");
446 482 }
447 483 }
484 +
485 + #ifdef SB_MAP_UNKNOWN_REGS
486 + static u32 sb_unk[256] = {0};
487 + static u32 sb_unk_ptr = 0;
488 +
489 + void sb_implement_unk(u32 loc,u32 base,const u32 size = 4)
490 + {
491 + base = (loc - base) >> 2;
492 +
493 + if(base >= 0x540)
494 + {
495 + log("sb_implement_unk : base(%u) out of range\n",base);
496 + return;
497 + }
498 +
499 + switch(size)
500 + {
501 + case 2:
502 + sb_regs[base].flags=REG_16BIT_READWRITE | REG_READ_DATA | REG_WRITE_DATA;
503 + sb_regs[base].data16=(u16*)(sb_unk + (sb_unk_ptr++));
504 + break;
505 +
506 + case 4:
507 + sb_regs[base].flags=REG_32BIT_READWRITE | REG_READ_DATA | REG_WRITE_DATA;
508 + sb_regs[base].data32=(u32*)(sb_unk + (sb_unk_ptr++));
509 + break;
510 +
511 + default:
512 + sb_regs[base].flags=REG_8BIT_READWRITE | REG_READ_DATA | REG_WRITE_DATA;
513 + sb_regs[base].data8=(u8*)(sb_unk + (sb_unk_ptr++));
514 + break;
515 + }
516 +
517 + sb_regs[base].readFunction=0;
518 + sb_regs[base].writeFunction=0;
519 + sb_regs[base].unk = 1;
520 + }
521 + #endif
522 +
448 523 void sb_Init()
449 524 {
450 525 sb_regs.Zero();
451 526
452 527 for (u32 i=0;i<sb_regs.Size;i++)
453 528 {
454 529 sb_regs.flags=REG_NOT_IMPL;
455 - }
530 +
531 + #ifdef SB_MAP_UNKNOWN_REGS
532 + sb_regs.unk = 0;
533 + #endif
534 + }
535 +
536 + #ifdef SB_MAP_UNKNOWN_REGS
537 + {
538 + //Unknown regs
539 + sb_unk_ptr = 0;
540 +
541 + sb_implement_unk(0x005f68a4,SB_BASE);
542 + sb_implement_unk(0x005f68ac,SB_BASE);
543 + sb_implement_unk(0x005f68a0,SB_BASE);
544 + sb_implement_unk(0x005f74a0,SB_BASE);
545 + sb_implement_unk(0x005f74a4,SB_BASE);
546 + sb_implement_unk(0x005f74a8,SB_BASE);
547 + sb_implement_unk(0x005f74ac,SB_BASE);
548 + sb_implement_unk(0x005f74b0,SB_BASE);
549 + sb_implement_unk(0x005f74b4,SB_BASE);
550 + sb_implement_unk(0x005f74e4,SB_BASE);
551 + sb_implement_unk(0x005f78a0,SB_BASE);
552 + sb_implement_unk(0x005f78a4,SB_BASE);
553 + sb_implement_unk(0x005f78a8,SB_BASE);
554 + sb_implement_unk(0x005f78ac,SB_BASE);
555 + sb_implement_unk(0x005f78b0,SB_BASE);
556 + sb_implement_unk(0x005f78b4,SB_BASE);
557 + sb_implement_unk(0x005f78b8,SB_BASE);
558 +
559 + sb_implement_unk(0x005f6b80,SB_BASE);
560 + sb_implement_unk(0x005f6b8c,SB_BASE);
561 + }
562 + #endif
456 563
457 564 sb_regs[((SB_C2DSTAT_addr-SB_BASE))>>2].flags=REG_32BIT_READWRITE | REG_READ_DATA | REG_WRITE_DATA;
458 565 sb_regs[((SB_C2DSTAT_addr-SB_BASE))>>2].readFunction=0;
...
