Major update - 68000 based unexpanded (with optional Slow or Fast RAM expansion) configurations are now 100% cycle-accurate - Big thanks to ross for writing test programs that required perfect cycle accuracy. Lots of expected and unexpected hardware features found and implemented Featute updates that got delayed but will be implemented in 5.0 - OCS and ECS Denise mid screen resolution changes are not pixel perfect, correct chip model specific bit pattern is not emulated yet. AGA is pixel perfect - Not all blitter line draw width != 2 (invalid line draw configuration, normally not used) conditions are 100% accurate - Disk status/interrupt timing is not fully confirmed yet New hardware emulation features and update - 68000 emulation is finally fully cycle accurate, last missing part, interrupt level change detection timing, is now cycle accurate - Custom chipset interrupt timing is now cycle accurate - CIA emulation is now fully cycle accurate. Timers were accurate previously but now also interrupt timing, TOD counting, CPU/E-clock sync, and more, including undocumented side-effects are cycle accurate - Serial port internal timing, interrupt timing, including SERDATR status bits are now cycle accurate (I used serial port interrupts as a timer in my cputester real 68000 interrupt timing tests) - Audio interrupt timing is now cycle accurate (Was almost fully accurate previously) - Blitter timing is now cycle accurate (previously startup behavior and interrupt timing was not fully accurate) - Blitter line mode with invalid settings (for example width not 2, octant and line direction mismatch etc) is now almost accurately emulated. Some conditions are not fully correct - Copper is now cycle accurate, previously some special cases were not handled correctly - More undocumented chipset features implemented - A1000 Denise bug emulated: sprites end horizontally 1 lores pixel later than bitplane horizontal window end. Currently enabled when A1000 Agnus is selected - OCS/ECS vs AGA EHB on/off mid screen change different behavior emulated - Emulated chipset mode display is blanked if programmed mode is active but has invalid configuration (for example too short or too long sync pulses or missing syncs, genlock sync enabled without genlock, etc) - Optional display mode change resync black screen delay - Programmed custom chipset modes again use also blanking timing to position the display in addition to vsync and hsync (Most real world SVGA monitors do the same) - Max allowed programmed mode non-interlaced vertical line count is now 800 (increased from 592), special 700+ line programmed modes are possible and compatible with real SVGA monitors - Refresh cycles conflicting with bitplane DMA is now accurately emulated, including all display and audio related glitches it can cause - Optional Chip RAM and Slow RAM power up pattern emulation, enabled by default - Color palette is now filled with pseudo-random contents at power up (was all black previously) - Monitor type selection. Composite sync or H/V sync. ECS Agnus/AGA programmed display modes can generate different C-Sync and H/V sync signals New other features and updates - RTG (uaegfx) Picasso96 v3.0+ mixed mode screen draggging is enabled by default - RTG (uaegfx) blitter emulation now supports previously unsupported less common blitter operations - RTG (uaegfx and emulated boards) automatic integer scaling support - On the fly FloppyBridge drive change to normal or back now triggers automatic disk change condition - Harddrive panel Full drive/RDB mode is now normal checbox. Hopefully it is less confusing than button that didn’t look like a button - Larger default GUI size and slightly larger font if Windows desktop is large enough (at least 1600*1024) - CD audio is now always mixed with Paula audio. Separate CD audio output support removed - Some American Laser Games didn’t have ROM descrambling support, also added missing ROM variants - Added American Laser Games Quickstart support - Added NVRAM path to Paths panel. Arcade/CD32/CDTV hardware NVRAM files default to this path - Keyboard reset change, reset state is kept until at least one key is released - CTRL+C in console log/debug window does not anymore close WinUAE. CTRL+C in newer Windows versions can be used as a Copy operation - Changed CTRL+F12 fullscreen/windowed switch: If already switched from full-window to window. Next CTRL+F12 will return back to full-window, not fullscreen - Optional interlace mode filter profile added - DirectDraw mode was replaced with GDI mode. GDI mode does not support exclusive fullscreen but supports basic scaling modes and uaegfx hardware cursor that DirectDraw mode did not support - Palette mode screenshot support. If enabled and screen has <= 256 colors, palette mode screenshot is created. It also attempts to preserve first 32 color entries if possible. RTC is automatically enabled if chipset extra= and system has fast ram, slow ram or chip ram expansion - Save MSM6242B RTC model control registers to RTC file if they are modified. Previously only RF5C01A (Used in big box Amigas) control registers (and NVRAM) was saved - If Quickstart ROM based Arcade hardware config (Arcadia or ALG) is selected, NVRAM file name is automatically set to ROM name. Genlock video file path is also set if ALG ROM is selected. Config files are not affected - ROM file list sorting changed, added grouping, sort by group priority first (KS ROMs, extended KS ROMs, freezer ROMs etc..), then alphabetically - Sometimes old graphics was temporarily visible in RTG modes if RTG had visible black borders (depends on scaling mode) and screen was switched and new screen had larger size/resolution - Added “Slow” flag to RAM panel. If set, selected memory bank has Chip RAM timing but is not Chip RAM capable. Advanced chipset panel “C00000 is Fast RAM” removed, it is not needed anymore 4.9.x bugs fixed - Sprite to playfield and playfield to playfield collisions were unreliable - RTG (uaegfx) overlay was not drawn. 32-bit Windows only - Magic mouse mode without virtual mouse driver installed: mouse position was incorrect in RTG modes and it also ignored scaling modes - If hardware emulated RTG board VRAM was immediately (no gap in address space) after any RAM/ROM region and JIT direct was enabled: first 4096 bytes (host CPU page size) of VRAM was not fully JIT direct compatible and any direct read or write to first 4096 bytes would not access VRAM correctly, causing unexpected graphics glitches - Quickstart panel floppy bootblock check used current track of drive (not track 0). Broken when FloppyBridge support was added - Hires resolution and hires BPLCON1 bit set (or shres and shres BPLCON1 bit): single pixel horizontal offset may have appeared in right side of screen. AGA and non-subpixel mode only - CD32/CDTV Quickstart mode “remembered” previous DF0: setting and didn’t disable it by default (even if Quickstart panel showed it as disabled) - CD32/CDTV Quickstart panel DF0: was not possible to select/enable - Z2 RAM configuration was unreliable Older bugs fixed - CHD CD image CD audio timing fix - Direct3D11 with custom shaders leaked memory - Directory filesystem softlinks fixed - 68060 without FPU or disabled FPU and executing FPU instruction that uses -(An) or (An)+ addressing mode: D7 was modified when exception stack frame was created - Reading from non-existing custom register always returned 0xFFFF instead of data that previous cycle’s possible DMA access transferred - Higher 68000/010 integer clock multipliers (4x+) in CE mode: chipset access timing was not accurate - Second 1M extended ROM bank is now internally split to two 512k banks. Non-aligned bank start and size caused problems in some configs - Hardware emulated RTG boards that have physically swapped red and blue output (Spectrum, Piccolo, Piccolo SD64) had wrong colors in 24/32-bit modes - Piccolo Z3 and Piccolo SD64 Z3 had wrong autoconfig board logical size (which crashed the driver) - CD audio was not resumed if WinUAE was unminimized and minimize was configured to pause emulation Debugging related updates and fixes - Ultra extreme overscan mode. Shows complete full raster including blanking regions. Horizontal and vertical blanking disabled. COLOR0 changes are always visible - DMA debugger shows CIA accesses (including cycles lost due to E-Clock sync) and Chip RAM RAS/CAS addressing values. - DMA debugger shows CPU memory access type (instruction fetch or data access). Interrupt level and interrupt level change detection are included - DMA debugger shows CPU opcodes in basic form (“NOP”, “MOVE” etc), vertically. Which can look a bit weird - Added CPU STOP state information to DMA debugger (| = STOP idle cycle, + = STOP idle cycle and higher IPL detected = STOP ending soon) - Visual DMA debugger shows conflicting cycles as blinking red pixels - Horizontal and vertical position are now included in debugger history output (H/HH) - Added OR, AND and XOR operators to debugger calculator (|, &, ^) - sp command parsed attached sprites incorrectly - It was not possible to enter debugger anymore if CPU was stuck in stopped state after entering and exiting the debugger once - Tracing STOP instruction now works differently, each single step executes one internal STOP “round” - Memwatch break point that crossed 64k “bank” didn’t map last 64k “bank” if it was only partially needed - Self modifying code (smc) debugger feature now clears detected modifications if 68020+ instruction cache is flushed - DMA debugger (both console and visual) better support for variable/toggling horizontal and vertical line counts